The present invention relates to a feedforward amplifier for amplifying a radio frequency signal and the like with suppressing signal error.
A feedforward amplifier that implements low error characteristic by feedforward error compensation is often used in radio frequencies such as VHF, UHF and microwave bands as an amplifier that can achieve low error amplification.
The feedforward error compensation scheme can achieve good error compensation principally, and has an advantage of being able to configure an amplifier with very low error. However, it has a problem of deteriorating its error characteristics because of reduction in the error compensation amount of a feedforward system caused by variations in the amplifier characteristics due to ambient temperature or secular changes.
To solve the problem, a system is proposed that introduces a pilot signal into a loop constituting the feedforward error compensation system, and controls the amplifier and loop of the feedforward system by detecting the pilot signal.
FIG. 1 is a block diagram showing a configuration of a conventional feedforward amplifier disclosed in Japanese patent application laid-open No. 4-70203, for example. In this figure, the reference numeral 1 designates an input terminal of the feedforward amplifier; 2 designates a pilot signal oscillator for generating a first pilot signal (frequency f1); 3 designates a combiner for combining an input signal supplied from the input terminal 1 with the first pilot signal; 4 designates a feedforward system; 5 designates a pilot signal oscillator for generating a second pilot signal (frequency f2); 6 designates an error detection loop for amplifying the input signal supplied from the combiner 3, and for extracting an error component involved in the amplification of the input signal; and 7 designates an error rejection loop for canceling out the error component included in the input signal.
The reference numeral 8 designates a divider for dividing the input signal plus the first pilot signal combined by the combiner 3 into two paths; 9 designates a vector regulator for electrically regulating passing amplitude and phase of the input signal distributed by the divider 8; 10 designates a combiner for combining the input signal supplied from the vector regulator 9 with the second pilot signal; 11 designates a main amplifier for amplifying the input signal passing through the combining by the combiner 10; 12 designates a delay circuit for delaying the input signal distributed by the divider 8; and 13 designates a dividing combiner for dividing the input signal output from the main amplifier 11 into two portions, for supplying a first portion of the input signal to a delay circuit 14, and for extracting the error component produced by the main amplifier 11 by canceling out the input signal component of a second portion of the input signal by combining the second portion of the input signal with the input signal delayed by the delay circuit 12.
The reference numeral 14 designates the delay circuit for delaying the input signal supplied from the dividing combiner 13; 15 designates a divider for distributing the error component extracted by the dividing combiner 13 to two paths; 16 designates a vector regulator for electrically regulating the passing amplitude and phase of the error component distributed by the divider 15; 17 designates an auxiliary amplifier for amplifying the error component output from the vector regulator 16; and 18 designates a combiner for combining the input signal delayed by the delay circuit 14 with the error component after the amplification, thereby canceling out the error component included in the input signal.
The reference numeral 19 designates a pilot signal detector for detecting the first pilot signal from the output signal of the divider 15; 20 designates a control circuit for controlling the vector regulator 9 such that the power level (signal level) of the first pilot signal detected by the pilot signal detector 19 becomes minimum; 21 designates a divider for distributing the input signal, the error component of which is canceled out by the combiner 18, to two paths; 22 designates a pilot signal detector for detecting the second pilot signal from the input signal distributed by the divider 21; 23 designates a control circuit for controlling the vector regulator 16 such that the power level (signal level) of the second pilot signal detected by the pilot signal detector 22 becomes minimum; 24 designates a bandpass filter (abbreviated to BPF from now on) for eliminating the first pilot signal from the input signal distributed by the divider 21; and 25 designates an output terminal of the feedforward amplifier.
Next, the operation will be described.
First, when the combiner 3 combines the input signal supplied from the input terminal 1 with the first pilot signal, the error detection loop 6 amplifies the input signal, and detects the error component involved in the amplification of the input signal.
Specifically, the divider 8 of the error detection loop 6 divides the input signal supplied from the combiner 3 to two paths. Then, the vector regulator 9 electrically regulates the passing amplitude and phase of a first portion of the input signal. After that, the combiner 10 combines the input signal with the second pilot signal, and the main amplifier 11 amplifies the input signal passing through the combining by the combiner 10.
On the other hand, the delay circuit 12 delays a second portion of the input signal divided by the divider 8 by a predetermined time period, and supplies it to the dividing combiner 13.
The dividing combiner 13, receiving the input signal amplified by the main amplifier 11, divides the input signal into two portions, and supplies the first portion of the input signal to the delay circuit 14. On the other hand, it combines the second portion of the input signal with the input signal supplied from the delay circuit 12. Thus, it extracts the error component the main amplifier 11 generates by canceling out the input signal component in the input signal after amplification.
Here, the error detection loop 6 performs optimization as follows.
Specifically, when the pilot signal detector 19 detects the first pilot signal from the output signal of the divider 15, the control circuit 20 controls the vector regulator 9 such that the power level of the first pilot signal becomes minimum, thereby optimizing the error detection loop 6.
The error rejection loop 7 cancels out the error component in the input signal when the error detection loop 6 extracts the error component from the input signal.
Specifically, when the vector regulator 16 of the error rejection loop 7 electrically regulates the passing amplitude and phase of the error component distributed by divider 15, and then the auxiliary amplifier 17 amplifies the error component, the combiner 18 combines the amplified error component with the input signal delayed through the delay circuit 14, thereby canceling out the error component in the input signal. Thus, the error component in the input signal is canceled out by combining the input signal with the error component with the identical amplitude and opposite phase to those of the error component in the amplified input signal.
The error rejection loop 7 performs optimization as follows.
Specifically, when the pilot signal detector 22 detects the second pilot signal in the output signal of the divider 21, the control circuit 23 controls the vector regulator 16 such that the power level of the second pilot signal becomes minimum, thereby optimizing the error rejection loop 7.
The BPF 24 rejects the first pilot signal included in one of the two portions output from the divider 21 that divides the combined input signal fed from the combiner 18 into two paths, and supplies the output terminal 25 only with the input signal component of the input signal.
As is clear from the foregoing description, optimizing the error detection loop 6 and the error rejection loop 7 constituting the feedforward error compensation system can implement the optimum error compensation regardless of the ambient temperature change or secular change.
However, the conventional example (referred to as conventional example 1 from now on) has the following problems.
Specifically, according to the conventional example 1, although the second pilot signal used for optimizing the error rejection loop 7 can be canceled out principally by the error rejection loop 7 because it is monitored at the output side of the feedforward system 4, the first pilot signal used for optimizing the error detection loop 6 cannot be canceled out principally because it is not monitored at the output side of the feedforward system 4 (it is monitored at the divider 15). For this reason, the BPF 24 is used for canceling out the first pilot signal.
The BPF 24, however, has a large size and high loss in general, thereby presenting a problem of hindering the feedforward amplifier from being miniaturized and made highly efficient. More specifically, to achieve precise control of the feedforward amplifier, the frequency of the pilot signal must be made as close as possible to the frequency of the input signal to be amplified.
The close frequencies, however, present a problem of increasing the size and loss of the BPF 24 because the BPF 24 must have such a characteristic as passing the amplified input signal and rejecting the pilot signal.
To solve the foregoing problem, a scheme of eliminating the first pilot signal used for optimizing the error detection loop 6 (it is called conventional example 2 from now on). The technique is disclosed in Japanese patent application laid-open No. 4-83407, for example. FIG. 2 is a block diagram showing a configuration of a conventional feedforward amplifier disclosed in Japanese patent application laid-open No. 4-83407. In this figure, the same reference numerals designate the same or like portions to those of FIG. 1, and hence the description thereof is omitted here.
The reference numeral 26 designates a vector regulator for electrically regulating the passing amplitude and phase of the first pilot signal; 27 designates a pilot signal amplifier for amplifying the first pilot signal; 28 designates a combiner for combining the first pilot signal with the input signal divided by the divider 21, thereby canceling out the first pilot signal in the input signal; 29 designates a divider for dividing the combined input signal supplied from the combiner 28; 30 designates a pilot signal detector for detecting the first pilot signal; and 31 designates a control circuit for controlling the vector regulator 26 such that the power level (signal level) of the first pilot signal detected by the pilot signal detector 30 becomes minimum.
According to the conventional example 2, when the divider 21 divides the input signal and outputs its part, and then the pilot signal amplifier 27 amplifies the first pilot signal as in the conventional example 1, the combiner 28 combines the first pilot signal with the input signal divided by the divider 21, thereby canceling out the first pilot signal in the input signal. Specifically, the first pilot signal contained in the input signal is canceled out by the first pilot signal with the identical amplitude and opposite phase to those of the first pilot signal in the input signal.
In this case, to increase the rejection accuracy of the first pilot signal, when the pilot signal detector 30 detects the first pilot signal from the output signal of the divider 29, the control circuit 31 controls the vector regulator 26 such that the power level of the first pilot signal becomes minimum.
The conventional example 2, however, comprises the pilot signal amplifier 27 for canceling out the first pilot signal. The pilot signal amplifier 27 brings about a rather large power consumption, and is used only for canceling out the pilot signal, thereby not contributing to the error compensation of the feedforward amplifier. Thus, although the error performance of the entire feedforward amplifier is not improved, its efficiency is decreased and its size is increased. In addition, the combiner 28, which is installed at the output side of the feedforward amplifier, causes a loss, offering a problem of reducing the efficiency and increasing the size of the device.
To avoid the problems involved in using the pilot signal to optimize the error detection loop 6 in the conventional examples 1 and 2, a technique is proposed that controls the vector regulator by detecting the level of the input signal itself without using the pilot signal to optimize the error detection loop 6, which is disclosed in Japanese patent application publication No. 7-77330.
However, when the input signal is not supplied or very small, the control of the error detection loop 6 is impossible. Accordingly, when the input signal increases sharply (such as in a burst operation of a mobile communication), the loop control lags behind it, thereby presenting a problem of temporarily deteriorating the performance of the feedforward amplifier.
With the foregoing configurations, the conventional feedforward amplifiers have the following problems. The conventional example 1, which comprises the BPF 24 to prevent the first pilot signal from being output from the output terminal 25, has a problem in that since the BPF 24 has a large size and high loss in general, it not only increases the size of the feedforward amplifier, but also reduces the efficiency thereof.
The conventional example 2, which cancels out the first pilot signal using the pilot signal amplifier 27 and combiner 28 to obviate the BPF 24 from its component, has a problem in that since the pilot signal amplifier 27 and combiner 28 have some power consumption and loss, they increase the size of the feedforward amplifier and reduces the efficiency thereof without improving the error characteristic of the feedforward amplifier.
The method that optimizes the error detection loop by detecting the level of the input signal itself has a problem of deteriorating the error characteristic temporarily in the burst operation or the like because it cannot perform optimization control when the input signal is not supplied or very small.
The present invention is implemented to solve the foregoing problems. Therefore, an object of the present invention is to provide a small-size, highly efficient feedforward amplifier capable of compensating for the error characteristic.
According to a first aspect of the present invention, there is provided a feedforward amplifier that combines the input signal combined by first error rejection means with an error component and a first pilot signal detected by second error detection means, thereby canceling out the error component and the first pilot signal residual in the input signal.
It offers an advantage of being able to compensate for the error characteristic at high efficiency with a small device size.
The feedforward amplifier in accordance with the present invention may adjust the amplitude and phase of the error component and the first pilot signal detected by the second error detection means to minimize a signal level of the first pilot signal.
It offers an advantage of being able to minimize the output of the first pilot signal.
The feedforward amplifier in accordance with the present invention may adjust the amplitude and phase of the input signal combined with the first pilot signal by the combining means to minimize a signal level of the first pilot signal.
It offers an advantage of being able to improve the compensation accuracy of the error characteristic.
The feedforward amplifier in accordance with the present invention may combine a second pilot signal with the input signal, the first error rejection means adjusts amplitude and phase of the error component and the second pilot signal detected by the first error detection means to minimize a signal level of the second pilot signal.
It offers an advantage of being able to improve the compensation accuracy of the error characteristic.
The feedforward amplifier in accordance with the present invention may adjust the amplitude and phase of the error component detected by the first error detection means to minimize a signal level of the error component.
It offers an advantage of being able to improve the compensation accuracy of the error characteristic.
The feedforward amplifier in accordance with the present invention may adjust the amplitude and phase of the input signal supplied to the combining means to minimize a signal level of an input signal component contained in the input signal combined by the first error rejection means.
It offers an advantage of being able to improve the compensation accuracy of the error characteristic.
The feedforward amplifier in accordance with the present invention may adjust, when the first error detection means combines a second pilot signal with the input signal, the amplitude and phase of the error component and the first and second pilot signals detected by the second error detection means to minimize a signal level of the first and second pilot signals.
It offers an advantage of being able to achieve good error compensation over a wide range.
The feedforward amplifier in accordance with the present invention may cause, when the amplitude and phase are controlled by the vector regulators in the first error detection means, in the first error rejection means and in the second error rejection means, the vector regulators to be each controlled by common control means.
It offers an advantage of being able to implement a low cost, small size feedforward amplifier.
The feedforward amplifier in accordance with the present invention may combine the first pilot signal with the input signal combined by the combining means to cancel out the first pilot signal contained in the input signal, and detect the error component and the first pilot signal by using the input signal in which the first pilot signal is canceled out.
It offers an advantage of being able to miniaturize the feedforward amplifier.
The feedforward amplifier in accordance with the present invention may further comprise in addition to the first and second error detection means and first and second error rejection means, at least one error detection means and at least one error rejection means to increase a number of stages of the error detection means and error rejection means to at least three.
It offers an advantage of being able to implement more satisfactory error compensation, thereby achieving a good error characteristic.